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Cycle-accurate HMC Thermal Simulation Framework

Introduction

Hybrid Memory Cube (HMC) is a high-performance Through-silicon vias-based stacked DRAM memory. HMC was first announced in 2011 by Micron Technology and promises a 15 times speed improvement over DDR3.

In this project, we propose a simulation framework to emulate the performance, power and temperature of the 3D stacked HMC-on-Processor structure.

Figure 1. An illustration of the 3D stacked HMC on processor structure

The simulation framework is illustrated in Figure 2. We use a CPU simulator (e.g. Gem5, Multi2Sim, etc.) to get the performance statistics of a program and generate the memory trace. McPAT is then used to generate the power of each module in the processor using the performance statistics. The kernel of this simulation framework is HMCTherm, a cycle-accurate HMC thermal simulator developed in our group. Currently, HMCTherm can take the CPU trace and the processor power profile as inputs to perform transient and steady-state thermal analysis using the in-house thermal model [1].

 

Figure 2. Simulation Framework

 

Download HMCTherm

The most updated version (v1.0) can be downloaded at https://github.com/zyyang1111/HMCTherm

 

Reference

[1] Shi, Bing, Ankur Srivastava, and Peng Wang. “Non-uniform micro-channel design for stacked 3D-ICs.” Proceedings of the 48th Design Automation Conference. ACM, 2011.